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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ad7910/ad7920 * 250 ksps, 10-/12-bit adcs in 6-lead sc70 features throughput rate: 250 ksps specified for v dd of 2.35 v to 5.25 v low power: 3.6 mw typ at 250 ksps with 3 v supplies 12.5 mw typ at 250 ksps with 5 v supplies wide input bandwidth: 71 db snr at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi /qspi/microwire/dsp compatible standby mode: 1 a max 6-lead sc70 package 8-lead msop package applications battery-powered systems personal digital assistants medical instruments mobile communications instrumentation and control systems data acquisition systems high speed modems optical sensors functional block diagram 10-/12-bit successive- approximation adc control logic ad7910/ad7920 gnd v dd v in sclk sdata cs t/h general description the ad7910/ad7920 are, respectively, 10-bit and 12-bit, high speed, low power, successive-approximation adcs. the parts operate from a single 2.35 v to 5.25 v power supply and feature throughput rates up to 250 ksps. the parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 mhz. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs and the conversion is also initiated at this point. there are no pipeline delays associated with the part. the ad7910/ad7920 use advanced design techniques to achieve very low power dissipation at high throughput rates. the reference for the part is taken internally from v dd. this allows the widest dynamic input range to the adc. thus the analog input range for the part is 0 to v dd . the conversion rate is determined by the sclk. product highlights 1. 10-/12-bit adcs in sc70 and msop packages. 2. low power consumption. 3. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. this allows the average power consumption to be reduced when power-down mode is used while not convert- ing. the part also features a power-down mode to maximize power efficiency at lower throughput rates. current consumption is 1 a max and 50 na typically when in power-down mode. 4. reference derived from the power supply. 5. no pipeline delay. the parts feature a standard successive-approximation adc with accurate control of the sampling instant via a cs input and once-off conversion control. * protected by u.s.patent no. 6,681,332.
rev. b ? ad7910?pecifications 1 (v dd = 2.35 v to 5.25 v, f sclk = 5 mhz, f sample = 250 ksps, t a = t min to t max , unless otherwise noted.) parameter a grade 1, 2 unit test conditions/comments dynamic performance f in = 100 khz sine wave signal-to-noise + distortion (sinad) 3 61 db min total harmonic distortion (thd) 3 ?2 db max peak harmonic or spurious noise (sfdr) 3 ?3 db max intermodulation distortion (imd) 3 second-order terms ?2 db typ fa = 100.73 khz, fb = 90.7 khz third-order terms ?2 db typ fa = 100.73 khz, fb = 90.7 khz aperture delay 10 ns typ aperture jitter 30 ps typ full power bandwidth 13.5 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 0.5 lsb max differential nonlinearity 0.5 lsb max guaranteed no missed codes to 10 bits offset error 3, 4 1lsb max gain error 3, 4 1lsb max total unadjusted error (tue) 3, 4 1.2 lsb max analog input input voltage ranges 0 to v dd v dc leakage current 0.5 m a max input capacitance 20 pf typ track-and-hold in track, 6 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input current, i in , sclk pin 0.5 m a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 na typ input capacitance, c in 5 5 pf max logic outputs output high voltage, v oh v dd ?0.2 v min i source = 200 m a, v dd = 2.35 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 m a floating-state leakage current 1 m a max floating-state output capacitance 5 5 pf max output coding straight (natural) binary conversion rate conversion time 2.8 m s max 14 sclk cycles with sclk at 5 mhz track-and-hold acquisition time 3 250 ns max throughput rate 250 ksps max power requirements v dd 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode(static) 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3 ma max v dd = 4.75 v to 5.25 v, f sample = 250 ksps 1.4 ma max v dd = 2.35 v to 3.6 v, f sample = 250 ksps full power-down mode 1 m a max typically 50 na power dissipation 6 normal mode (operational) 15 mw max v dd = 5 v, f sample = 250 ksps 4.2 mw max v dd = 3 v, f sample = 250 ksps full power-down 5 m w max v dd = 5 v 3 m w max v dd = 3 v notes 1 temperature range from ?0 c to +85 c. 2 operational from v dd = 2.0 v, with input high voltage (v inh ) 1.8 v min. 3 see terminology section. 4 sc70 values guaranteed by characterization. 5 guaranteed by characterization. 6 see power vs. throughput rate section. specifications subject to change without notice.
rev. b ad7910/ad7920 ? ad7920?pecifications 1 (v dd = 2.35 v to 5.25 v, f sclk = 5 mhz, f sample = 250 ksps, t a = t min to t max , unless otherwise noted.) parameter a grade 1, 2 b grade 1, 2 unit test conditions/comments dynamic performance f in = 100 khz sine wave signal-to-noise + distortion (sinad) 3 70 70 db min v dd = 2.35 v to 3.6 v, t a = 25 c 69 69 db min v dd = 2.4 v to 3.6 v 71.5 71.5 db typ v dd = 2.35 v to 3.6 v 69 69 db min v dd = 4.75 v to 5.25 v, t a = 25 c 68 68 db min v dd = 4.75 v to 5.25 v signal-to-noise ratio (snr) 3 71 71 db min v dd = 2.35 v to 3.6 v, t a = 25 c 70 70 db min v dd = 2.4 v to 3.6 v 70 70 db min v dd = 4.75 v to 5.25 v, t a = 25 c 69 69 db min v dd = 4.75 v to 5.25 v total harmonic distortion (thd) 3 ?0 ?0 db typ peak harmonic or spurious noise (sfdr) 3 ?2 ?2 db typ intermodulation distortion (imd) 3 second-order terms ?4 ?4 db typ fa = 100.73 khz, fb = 90.72 khz third-order terms ?4 ?4 db typ fa = 100.73 khz, fb = 90.72 khz aperture delay 10 10 ns typ aperture jitter 30 30 ps typ full power bandwidth 13.5 13.5 mhz typ @ 3 db 22 mhz typ @ 0.1 db dc accuracy b grade 4 resolution 12 12 bits integral nonlinearity 3 1.5 lsb max 0.75 lsb typ differential nonlinearity ?.9/+1.5 lsb max guaranteed no missed codes to 12 bits 0.75 lsb typ offset error 3, 5 1.5 lsb max 1.5 0.2 lsb typ gain error 3, 5 1.5 lsb max 1.5 0.5 lsb typ total unadjusted error (tue) 3,5 2 lsb max analog input input voltage ranges 0 to v dd 0 to v dd v dc leakage current 0.5 0.5 m a max input capacitance 20 20 pf typ track-and-hold in track, 6 pf typ when in hold logic inputs input high voltage, v inh 2.4 2.4 v min 1.8 1.8 v min v dd = 2.35 v input low voltage, v inl 0.8 0.8 v max v dd = 3.6 v to 5.25 v 0.4 0.4 v max v dd = 2.35 v to 3.6 v input current, i in , sclk pin 0.5 0.5 m a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 10 na typ input capacitance, c in 6 5 5pf max logic outputs output high voltage, v oh v dd ?0.2 v dd ?0.2 v min i source = 200 m a, v dd = 2.35 v to 5.25 v output low voltage, v ol 0.4 0.4 v max i sink = 200 m a floating-state leakage current 1 1 m a max floating-state output capacitance 6 55pf max output coding straight (natural) binary conversion rate conversion time 3.2 3.2 m s max 16 sclk cycles with sclk at 5 mhz track-and-hold acquisition time 3 250 250 ns max throughput rate 250 250 ksps max see serial interface section
rev. b ? ad7910/ad7920 ad7910/ad7920 parameter limit at t min, t max unit description f sclk 2 10 khz min 3 5 mhz max t convert 14 t sclk ad7910 16 t sclk ad7920 t quiet 50 ns mi nm inimum quiet time required between bus relinquish and start of next conversion t 1 10 ns min minimum cs pulse width t 2 10 ns min cs to sclk setup time t 3 4 22 ns max delay from cs until sdata three-state disabled t 4 4 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk ns min sclk high pulse width t 7 5 sclk to data valid hold time 10 ns min v dd 3.3 v 9.5 ns min 3.3 v < v dd 3.6 v 7 ns min v dd > 3.6 v t 8 6 36 ns max sclk falling edge to sdata three-state see note 7 ns min sclk falling edge to sdata three-state t power-up 8 1 m s max power-up time from full power-down notes 1 guaranteed by characterization. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 minimum f sclk at which specifications are guaranteed. 4 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 1.8 v when v dd = 2.35 v and 0.8 v or 2.0 v for v dd > 2.35 v. 5 measured with a 50 pf load capacitor. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 t 7 values apply to t 8 minimum values also. 8 see power-up time section. specifications subject to change without notice. ad7920?pecifications 1 (continued) parameter a grade 1, 2 b grade 1, 2 unit test conditions/comments power requirements v dd 2.35/5.25 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 2.5 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3 3 ma max v dd = 4.75 v to 5.25 v, f sample = 250 ksps 1.4 1.4 ma max v dd = 2.35 v to 3.6 v, f sample = 250 ksps full power-down mode 1 1 m a max typically 50 na power dissipation 7 normal mode (operational) 15 15 mw max v dd = 5 v, f sample = 250 ksps 4.2 4.2 mw max v dd = 3 v, f sample = 250 ksps full power-down 5 5 m w max v dd = 5 v 33 m w max v dd = 3 v notes 1 temperature range from ?0 c to +85 c. 2 operational from v dd = 2.0 v, with input low voltage (v inl ) 0.35 v max. 3 see terminology section. 4 b grade, maximum specs apply as typical figures when v dd = 4.75 v to 5.25 v. 5 sc70 values guaranteed by characterization. 6 guaranteed by characterization. 7 see power vs. throughput rate section. specifications subject to change without notice. timing specifications 1 ( v dd = 2.35 v to 5.25 v, t a = t min to t max , unless otherwise noted.)
rev. b ad7910/ad7920 ? cs sclk sdata t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t q uiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 12 345 13 14 15 16 t 1 figure 2. ad7920 serial interface timing diagram cs sclk t 2 t convert b 1 2345 13141516 c t 8 t q uiet t acq 12.5(1/f sclk ) 1/throughput figure 3. serial interface timing example to output pin c l 50pf 200 a i oh 200 a i ol 1.6v figure 1. load circuit for digital output timing specifications timing examples figures 2 and 3 show some of the timing parameters from the timing specifications table. timing example 1 from f igure 3, having f sclk = 5 mhz and a throughput rate of 250 ksps gives a cycle time of t 2 + 12.5(1/f sclk ) + t acq = 4 m s. with t 2 = 10 ns min, this leaves t acq to be 1.49 m s. this 1.49 m s satisfies the requirement of 250 ns for t acq . from figure 3, t acq comprises 2.5(1/f sclk ) + t 8 + t quiet , where t 8 = 36 ns max. this allows a value of 954 ns for t quiet, satisfying the minimum re- quirement of 50 ns. timing example 2 the ad7920 can also operate with slower clock frequencies. from figure 3, having f sclk = 3.4 mhz and a throughput rate of 150 ksps gives a cycle time of t 2 + 12.5(1/f sclk ) + t acq = 6.66 m s. with t 2 = 10 ns min, this leaves t acq to be 2.97 m s. this 2.97 m s satisfies the requirement of 250 ns for t acq . from fi g ure 3, t acq comprises 2.5(1/f sclk ) + t 8 + t quiet , t 8 = 36 ns max. t his allows a value of 2.19 m s for t quiet , satisfying the minimum requirement of 50 ns. as in this example and with other slower clock values, the signal may already be acquired before the con version is complete, but it is still necessary to leave 50 ns minimum t quiet between conversions. in this example, the signal should be fully acquired at approximately point c in figure 3.
rev. b ? ad7910/ad7920 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7910/ad7920 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v analog input voltage to gnd . . . . . . . ?.3 v to v dd + 0.3 v digital input voltage to gnd . . . . . . . . . . . . . ?.3 v to +7 v digital output voltage to gnd . . . . . ?.3 v to v dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial (a, b grade) . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c msop package q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 205.9 c/w q jc thermal impedance . . . . . . . . . . . . . . . . . . . . 43.74 c/w sc70 package q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 340.2 c/w q jc thermal impedance . . . . . . . . . . . . . . . . . . . . 228.9 c/w lead temperature, soldering reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . 235 (0/+5) c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide temperature linearity package model range error (lsb) 1 option 2 branding AD7910AKS-500RL7 ?0 c to +85 c 0.5 max ks-6 cva ad7910aks-reel ?0 c to +85 c 0.5 max ks-6 cva ad7910aks-reel7 ?0 c to +85 c 0.5 max ks-6 cva ad7910arm ?0 c to +85 c 0.5 max rm-8 cva ad7910arm-reel ?0 c to +85 c 0.5 max rm-8 cva ad7910arm-reel7 ?0 c to +85 c 0.5 max rm-8 cva ad7920aks-500rl7 ?0 c to +85 c 0.75 typ ks-6 cua ad7920aks-reel ?0 c to +85 c 0.75 typ ks-6 cua ad7920aks-reel7 ?0 c to +85 c 0.75 typ ks-6 cua ad7920bks ?0 c to +85 c 1.5 max ks-6 cub ad7920bks-reel ?0 c to +85 c 1.5 max ks-6 cub ad7920bks-reel7 ?0 c to +85 c 1.5 max ks-6 cub ad7920brm ?0 c to +85 c 1.5 max rm-8 cub ad7920brm-reel ?0 c to +85 c 1.5 max rm-8 cub ad7920brm-reel7 ?0 c to +85 c 1.5 max rm-8 cub eval-ad7910cb 3 evaluation board eval-ad7920cb 3 evaluation board eval-control brd2 4 notes 1 linearity error refers to integral nonlinearity. 2 ks = sc70, rm = msop. 3 this can be used as a stand-alone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstration pu rposes. 4 this board is a complete unit that allows a pc to control and communicate with all analog devices evaluation boards ending in t he cb designator. to order a complete evaluation kit, a particular adc evaluation board must be ordered, e.g., eval-ad7920cb, the eval-control brd2, and a 1 2 v ac transformer. see relevant evaluation board technical note for more information.
rev. b ad7910/ad7920 ? pin function descriptions mnemonic function cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7910/ ad7920 and framing the serial data transfer. v dd power supply input. the v dd range for the ad7910/ad7920 is from 2.35 v to 5.25 v. gnd analog ground. ground reference point for all circuitry on the ad7910/ad7920. all analog input signals should be referred to this gnd voltage. v in analog input. single-ended analog input channel. the input range is 0 to v dd . sdata data out. logic output. the conversion result from the ad7910/ad7920 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the ad7920 consists of four leading zeros followed by the 12 bits of conversion data, which is provided msb first. the data stream from the ad7910 consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided msb first. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7910/ad7920 conversion process. nc no connect pin configurations 6-lead sc70 top view (not to scale) 6 5 4 1 2 3 v dd gnd v in cs sdata sclk ad7910/ ad7920 8-lead msop 8 7 6 5 1 2 3 4 v dd sdata cs v in gnd sclk nc nc top view (not to scale) ad7910/ ad7920 nc = no connect
rev. b ? ad7910/ad7920 terminology integral nonlinearity t he maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the ad7920 and ad7910, the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity th e difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error th e deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., gnd + 1 lsb. gain error the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e., v ref ?1 lsb after the offset error has been adjusted out. track-and-hold acquisition time the track-and-hold amplifier r eturns to track mode at the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion. see the serial interface section for more details. signal-to-(noise + distortion) ratio t he measured ratio of signal-to-(noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to- noise distortion n ()(..) +=+ 602 1 76 db thus, for a 12-bit converter this is 74 db, and for a 10-bit converter this is 62 db. total unadjusted error a comprehensive specification that includes gain error, linearity error, and offset error. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of har- monics to the fundamental. it is defined as: thd vvvvv v 2 2 3 2 4 2 5 2 6 2 1 () lo g db = + +++ 20 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spec- trum (up to f s /2 and excluding dc) to the rms value of the funda- mental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs whose har- monics are buried in the noise floor, it w ill be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ?fb), while the third order terms include (2fa + fb), (2fa ?fb), (fa + 2fb), and (fa ?2fb). the ad7910/ad7920 are tested using the ccif standard, where two input frequencies are used (see fa and fb in the specification page). in this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the funda- mentals, expressed in db.
rev. b t ypical performance characteristics?d7910/ad7920 ? tpc 1 and tpc 2 show a typical fft plot for the ad7920 and ad7910, respectively, at a 250 ksps sampling rate and a 100 khz input frequency. tpc 3 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 250 ksps with a sclk frequency of 5 mhz for the ad7920. tpc 4 and tpc 5 show typical inl and dnl performance for the ad7920. frequency (khz) ? ?5 ?15 0 125 25 snr (db) 50 75 100 ?5 ?5 ?5 ?5 8192 point fft v dd = 2.7v f sample = 250ksps f in = 100khz sinad = 72.05db thd = ?2.87db sfdr = ?7.24db tpc 1. ad7920 dynamic performance at 250 ksps frequency (khz) ?5 ?05 snr (db) ? ?5 ?5 ?5 8192 point fft v dd = 2.35v f sample = 250ksps f in = 100khz sinad = 61.67db thd = ?9.59db sfdr = ?2.93db 0 125 25 50 75 100 tpc 2. ad7910 dynamic performance at 250 ksps frequency (khz) ?2.0 10 1000 sinad (db) 100 ?3.0 ?3.5 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v ?2.5 ?1.0 ?1.5 tpc 3. ad7920 sinad vs. input frequency at 250 ksps code 1.0 0.4 ?.2 0 1024 inl error (lsb) 512 0.8 0.6 0.2 0 ?.4 ?.6 ?.8 ?.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25 c f sample = 250ksps tpc 4. ad7920 inl performance tpc 6 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of 3.6 v and sampling at a rate of 250 ksps. see the analog input section. tpc 7 shows a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 250 ksps with an sclk frequency of 5 mhz.
rev. b ?0 ad7910/ad7920 circuit information the ad7910/ad7920 are fast, micropower, 10-bit/12-bit, single-supply a/d converters, respectively. the parts can be operated from a 2.35 v to 5.25 v supply. when operated from either a 5 v supply or a 3 v supply, the ad7910/ad7920 are capable of throughput rates of 250 ksps when provided with a 5 mhz clock. the ad7910/ad7920 provide the user with an on-chip track- and-hold, a/d converter, and a serial interface housed in a tiny 6-lead sc70 package or 8-lead msop package, which offers the user considerable space saving advantages over alternative solu- tions. the serial clock input accesses data from the part but also provides the clock source for the successive-approximation a/d converter. the analog input range is 0 v to v dd . an external reference is not required for the adc and there is no reference on-chip. the reference for the ad7910/ad7920 is derived from the power supply and thus gives the widest dynamic input range. the ad7910/ad7920 also feature a power-down option to allow power saving between conversions. the power-down feature is implemented across the standard serial interface, as described in the modes of operation section. converter operation the ad7910/ad7920 is a successive-approximation analog- to-digital converter based around a charge redistribu tion dac. figures 4 and 5 show simplified schematics of the adc. fig ure 4 shows the adc during its acquisition phase. when sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on v in . charge redistribution dac control logic comparator sw2 sampling capacitor acq uisition phase sw1 a b a gnd v dd /2 v in figure 4. adc acquisition phase code 1.0 0.4 ?.2 0 1024 dnl error (lsb) 512 0.8 0.6 0.2 0 ?.4 ?.6 ?.8 ?.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25 c f sample = 250ksps tpc 5. ad7920 dnl performance input frequency (khz) ?0 ?0 10 1000 thd (db) 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 v dd = 3.6v r in = 10k r in = 1k r in = 130 r in = 13 r in = 0 tpc 6. thd vs. analog input frequency for various source impedances input frequency (khz) ?5 ?0 10 1000 thd (db) 100 ?5 ?0 ?0 ?5 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v tpc 7. thd vs. analog input frequency for various supply voltages
rev. b ad7910/ad7920 ?1 when the adc starts a conversion (see figure 5), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and charge redistribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 6 shows the adc transfer function. charge redistribution dac control logic comparator sw2 sampling capacitor conversion phase sw1 a b a gnd v dd /2 v in figure 5. adc conversion phase adc transfer function the output coding of the ad7910/ad7920 is straight binary. the designed code transitions occur at the successive integer lsb values, i.e., 1 lsb, 2 lsbs, and so on. the lsb size is v dd /4096 for the ad7920 and v dd /1024 for the ad7910. the ideal transfer characteristic for the ad7910/ad7920 is shown in figure 6. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb +v dd ?lsb 1lsb = v dd /1024 (ad7910) 1lsb = v dd /4096 (ad7920) figure 6. transfer characteristic typical connection diagram figure 7 shows a typical connection diagram for the ad7910/ ad7920. v ref is taken internally from v dd and, as such, v dd should be well decoupled. this provides an analog input range of 0 v to v dd . the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit or 10-bit result. the 10-bit result from the ad7910 will be followed by two trailing zeros. alternatively, because the supply current required by the ad7910/ ad7920 is so low, a precision reference can be used as the supply source to the ad7910/ad7920. an ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) can be used to supply the required voltage to the adc (see figure 7). this con- figuration is especially useful if the power supply is quite noisy or if the system supply voltages are at a value other than 5 v or 3v (e.g., 15 v). the ref19x will output a steady voltage to the ad7910/ad7920. if the low dropout ref193 is used, the current it needs to supply to the ad7910/ad7920 is typically 1.2 ma. when the adc is converting at a rate of 250 ksps the ref193 needs to supply a maximum of 1.4 ma to the ad7910/ad7920. the load regulation of the ref193 is typically 10 ppm/ma (ref193, v s = 5 v), which results in an error of 14 ppm (42 m v) for the 1.4 ma drawn from it. this corresponds to a 0.057 lsb error for the ad7920 with v dd = 3 v from the ref193 and a 0.014 lsb error for the ad7910. for applications where power consumption is of concern, the power-down mode of the adc and the sleep mode of the ref19x reference should be used to improve power performance. see the modes of operation section. ad7910/ ad7920/ sclk sdata cs v in gnd 0v to v dd input v dd c/ p serial interface 0.1 f 1 f t ant ref193 1.2ma 680nf 10 f 0.1 f 3v 5v supply figure 7. ref193 as power supply table i provides typical performance data with various references used as a v dd source for a 100 khz input tone at room temper- ature under the same setup conditions. table i. ad7920 typical performance for various voltage references ic reference ad7920 snr tied to v dd performance (db) ad780 @ 3 v 72.65 ref193 72.35 ad780 @ 2.5 v 72.5 ref192 72.2 ref43 72.6
rev. b ?2 ad7910/ad7920 analog input figure 8 shows an equivalent circuit of the analog input structure of the ad7910/ad7920. the two diodes d1 and d2 provide esd protection for the analog input. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 10 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. the capacitor c1 in figure 8 is typically about 6 pf and can be attributed primarily to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 100 w . the capacitor c2 is the adc sampling capacitor and has a capacitance of 20 pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by use of a band-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal- to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will signifi- cantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. d1 d2 r1 c2 20pf v dd v in c1 6pf conversion phase ?switch open track phase ?switch closed figure 8. equivalent analog input circuit table ii provides some typical performance data with various op amps used as the input buffer for a 100 khz input tone at room temperature under the same setup conditions. table ii. ad7920 typical performance for various input buffers, v dd = 3 v op amp in the ad7920 snr input buffer performance (db) ad711 72.3 ad797 72.5 ad845 71.4 w hen no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases, and performance degrades (see tpc 6). digital inputs the digital inputs applied to the ad7910/ad7920 are not limited by the maximum ratings that limit the analog input. instead, the digital inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog input. for example, if the ad7910/ad7920 were operated with a v dd of 3v , then 5 v logic levels could be used on the digital inputs. how ever, it is important to note that the data output on sdata will still have 3 v logic levels when v dd = 3 v. another advantage of sclk and cs not being restricted by the v dd + 0.3 v lim it is that power supply sequencing issues are avoided. if cs or sclk is applied before v dd , there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v was applied prior to v dd . modes of operation the mode of operation of the ad7910/ad7920 is selected by controlling the logic state of the cs signal during a conver sion. there are two possible modes of operation, normal mode and p ower-down mode. the point at which cs is pulled high after the conversion has been initiated determines whether the ad7910/ad7920 enters power-down mode. similarly, if the device is al ready in power-d own mode, cs can control whether it returns to normal operation or remains in pow er-down mode. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differ ent applica- tion requirements. normal mode this mode is intended for fastest throughput rate performance because the user does not have to worry about any power-up tim es; the ad7910/ad7920 remains fully powered all the time. figure 9 shows the general diagram of the operation of the ad7910/ad7920 in this mode. the conversion is initiated on the falling edge of cs as described in the serial interface section. to ensure that the part remains fully powered up at all times, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge but before the end of the t convert , the part will remain pow- ered up but the conversion will be terminated and sdata will go back into three-state. for the ad7920, 16 serial clock cycles are required to com plete the conversion and access the complete conversion result. for the ad7910, a minimum of 14 serial clock cycles is required to com- plete the conversion and access the comp lete conv ersion result. cs may idle high until the next conversion or may idle low until cs returns high som etime prior to the next conversion, effectively idling cs low. once a data transfer is complete (sdata has returned to three- state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again.
rev. b ad7910/ad7920 ?3 power-down mode this mode is intended for use in applications where slower through- put rates are required; either the adc is powered down between conversions, or a series of conversions may be performed at a high throughput rate and the adc is powered down for a rela- tively long duration between these bursts of several conversions. when the ad7910/ad7920 is in power-down mode, all analog circuitry is pow ered down. to enter power-down mode, the conversion process must be inter rupted by bringing cs high anywhere after the second falling edge of sclk, and before the 10th falling edge of sclk as shown in figure 10. once cs has been brought high in this window of sclks, the part will enter power-down mode, the conversion that was initiated by the falling edge of cs will be terminated, and s data will go back into three-state. if cs is brought high before the second sclk falling edge, the part will remain in normal mode and will not power down. this will avoid accidental power- down due to glitches on the cs line. to exit this mode of operation and power up the ad7910/ad7920 again, a dummy conversion is performed. on the falling edge of cs , the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the 10th sclk. the device will be fully powered up once 16 sclks have elapsed and valid data will result from the next conversion, as shown in figure 11. if cs is brought high before the 10th sclk falling edge, the ad7910/ad7920 will go back into power-down mode again. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. although the device may begin to power up on the falling edge of cs , it will power down again on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power-up time the power-up time of the ad7910/ad7920 is 1 m s, which means that one dummy cycle will always be sufficient to allow the device to power up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be acquired prop erly. the quiet time, t quiet , must still be allowed from the point w here the bus goes back into three-state after the dummy conversion, to the next falling edge of cs . when powering up from the power-down mode with a dummy cycle, as in figure 11, the track-and-hold that was in hold mode while the part was powered down returns to track mode after va l id data sdata sclk cs 110121 416 ad7910/ad7920 figure 9. normal mode operation three-state sdata sclk cs 110121 416 2 figure 10. entering power-down mode invalid data sdata sclk cs 110121416 a 116 va l id data the part is fully powered up with v in fully acquired the part begins to power up figure 11. exiting power-down mode
rev. b ?4 ad7910/ad7920 the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 11. although at any sclk frequency one dummy cycle is sufficient to power up the device and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and fully acquire v in ; 1 s will be sufficient to power the device up and acquire the input signal. so, if a 5 mhz sclk frequency is applied to the adc, the cycle time will be 3.2 s. in one dummy cycle, 3.2 s, the part will be powered up and v in fully acquired. however, after 1 m s with a 5 mhz sclk, only five sclk cycles will have elapsed. at this stage, the adc will be fully powered up and the signal acquired. in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the ad7910/ad7920, the adc may power up in either power down mode or in normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if the intention is to keep the part in power-down mode while not in use and the user wishes the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 10. once supplies are applied to the ad7910/ad7920, the power-up time is the same as that when powering up from power-down mode. it takes approximately 1 s to power up fully if the part powers up in normal mode. it is not necessary to wait 1 m s before executing a dummy cycle to ensure th e desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is performed directly after the dummy conversion, care must be taken to ensure that adequate acquisi- tion time is allowed. as mentioned earlier, when powering up from the pow er-down mode, the part will return to track upon the first s clk edge applied after the falling edge of cs . how- ever when the adc powers up initially after supplies are applied, the track-and-hold will already be in track. this means, assuming one has the facility to monitor the adc supply cur- rent, if the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, neither is a dummy cycle required to place the track-and-hold into track. power vs. throughput rate by using the power-down mode on the ad7910/ad7920 when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 12 shows how, as the throughput rate is reduced, the device remains in its power- dow n state longer and the average power consumption over time drops accordingly. for example, if the ad7910/ad7920 is operated in a continuous sampling mode with a throughput rate of 100 ksps and an sclk of 5 mhz (v dd = 5 v), and the device is placed in the power- do wn mode between conversions, the power consumption is calculated as follows: the power dissipation during normal mode is 15 mw (v dd = 5 v). the power dissipation includes the power dissipated while the part is entering power-down mode, the power dissi pated during the dummy conversion (when the part is exiting power-down mode and powering up), and the power dissipated during conversion. as mentioned in the power-down mode section, to enter power- down mode, cs has to be brought high anywhere betw een the second and 10th sclk falling edge. therefore, the power con- sumption when entering power-down mode will vary depending on the number of sclk cycles used. in this example, five sclk cycles will be used to enter power-down mode. this gives a time period of 5 (1/f sclk ) = 1 s. the power-up time is 1 s, which implies that only five sclk cycles are required to power up the part. however, cs has to remain low until at least the 10th sclk falling edge when exiting power-down mode. this means that a minimum of nine sclk cycles have to be used to exit power-down mode and power up the part. so, if nine sclk cycles are used, the time to power up the part and exit power-down mode is 9 (1/f sclk ) = 1.8 s. finally, the conversion time is 16 (1/f sclk ) = 3.2 s. therefore, the ad7910/ad7920 can be said to dissipate 15 mw for 3.2 s + 1.8 s + 1 s = 6 s during each conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is (6/10) (15 mw) = 9 mw. the power dissipation when the part is in power-down has not been taken into account as the shutdown current is so low and it does not have any effect on the overall power dissipation value. if v dd = 3 v, sclk = 5 mhz and the device is again in power- down mode between conversions, the power dissipation during normal operation is 4.2 mw. assuming the same timing condi- tions as before, the ad7910/ad7920 can now be said to dissipate 4.2 mw for 6 m s during each conversion cycle. with a throughput rate of 100 ksps, the average power dissipated during each cycle is (6/10) (4.2 mw) = 2.52 mw. figure 12 shows the power versus throughput rate when using the power-down mode between conversions with both 5 v and 3 v supplies. power-down mode is intended for use with throughput rates of approximately 160 ksps and under, because at higher sampling rates there is no power saving made by using the power-down mode. throughput rate (ksps) 100 0.1 0 power (mw) 10 1 0.01 20 v dd = 5v, sclk = 5mhz v dd = 3v, sclk = 5mhz 40 60 80 100 120 140 160 180 figure 12. power vs. throughput rate
rev. b ad7910/ad7920 ?5 serial interface figures 13 and 14 show the detailed timing diagram for serial interfacing to the ad7920 and ad7910, respectively. the serial clock provides the conversion clock and also controls the transfer of information from the ad7910/ad7920 during conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state; the analog input is sampled at that point. the conversion is also initiated at this point. for the ad7920, the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, track-and- hold goes back into track on the next sclk rising edge as shown in figure 13 at point b. on the 16th sclk falling edge, the sdata line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, then the conversion is terminated and the sdata line goes back into three-state; otherwise, sdata returns to three-state on the 16th sclk falling edge, as shown in figure 13. sixteen serial clock cycles are required to perform the conversion process and to access data from the ad7920. for the ad7910, the conversion requires 14 sclk cycles to complete. once 13 sclk falling edges have elapsed, track-and- hold goes back into track on the next sclk rising edge, as shown in figure 14 at point b. if the rising edge of cs occurs before 14 sclks have elapsed, the conversion is terminated and the sdata line goes back into three-state. if 16 sclks are used in the cycle, sdata returns to three-state on the 16th sclk falling edge, as shown in figure 14. cs going low clocks out the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the sec- ond leading zero. thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge. in this case, the first falling edge of sclk will clock out the second leading zero, which could be read in the first rising edge. however, the first leading zero that was clocked out when cs went low will be missed unless it was not read in the first falling edge. the 15th falling edge of sclk will clock out the last bit and it could be read in the 15th rising sclk edge. if cs goes low just after the sclk falling edge has elapsed, cs clocks out the first leading zero as before, and it may be read on the sclk rising edge. the next sclk falling edge clocks out the second leading zero and it could be read on the following rising edge. cs sclk sdata t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t q uiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 12 345 13 14 15 16 t 1 1/throughput figure 13. ad7920 serial interface timing diagram sclk 1 5 13 15 4 leading zeros three-state t 4 2 34 16 t 5 t 3 t 2 db9 db8 db0 zero t 6 t 7 t 8 14 zero zero zero z t 1 zero 2 trailing zeros sdata t q uiet b three-state cs t convert 1/throughput figure 14. ad7910 serial interface timing diagram
rev. b ?6 ad7910/ad7920 microprocessor interfacing the serial interface on the ad7910/ad7920 allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the ad7910/ad7920 with some of the more common microcontroller and dsp serial interface protocols. ad7910/ad7920 to tms320c541 interface the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7910/ ad7920. the cs input allows easy interfacing between the tms320c541 and the ad7910/ad7920 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode (fsm = 1 in the serial port control register, spc) with internal serial clock clkx (mcm = 1 in spc register) and internal frame signal (txm = 1 in the spc), so both pins are configured as outputs. for the ad7920, the word length should be set to 16 bits (fo = 0 in the spc register). this dsp allows frames with a word length of 16 or 8 bits. therefore, in the case of the ad7910 where just 14 bits could be required, the fo bit would be set up to 16 bits also. this means that to obtain the conversion result, 16 sclks are needed and two trailing zeros will be clocked out in the two last clock cycles. to summarize, the values in the spc register are: fo = 0 fsm = 1 mcm = 1 txm = 1 the format bit, fo, may be set to 1 to set the word length to eight bits, in order to implement the power-down mode on the ad7910/ad7920. the connection diagram is shown in figure 15. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 provides equidistant sampling. ad7910/ad7920 * sclk sdata cs clkx clkr fsx fsr tms320c541 * * additional pins omitted for clarity dr figure 15. interfacing to the tms320c541 ad7910/ad7920 to adsp-218x the adsp-218x family of dsps is interfaced directly to the ad7910/ad7920 without any glue logic required. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, sets up rfs as an input itfs = 1, sets up tfs as an output slen = 1111, 16 bits for the ad7920 slen = 1101, 14 bits for the ad7910 to implement power-down mode, slen should be set to 0111 to issue an 8-bit sclk burst. the connection diagram is shown in figure 16. the adsp-218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame syn- chronization signal generated on the tfs is tied to cs and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc and, under certain conditions, equidistant sampling may not be achieved. the timer registers are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to contro l t he rfs an d thus the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transm it with tfs is given, i.e., tx0 = ax0, the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high before trans- mission starts. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data may be transmitted or it may wait until the next clock edge. for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value 3, an sclk of 2 mhz is obtained and eight master clock periods will elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks will occur between interrupts and subsequently between transmit instructions. this situation will result in nonequidistant sampling as the transmit instruc tion is occurring on an sclk edge. if the number of sclks between interrupts is a whole integer figure of n, equidistant sampling will be implemented by the dsp. ad7910/ad7920 * sclk sdata cs sclk dr rfs tfs adsp-218x * * additional pins omitted for clarity figure 16. interfacing to the adsp-218x
rev. b ad7910/ad7920 ?7 ad7910/ad7920 to dsp563xx interface the diagram in figure 17 shows how the ad7910/ad7920 can be connected to the ssi (synchronous serial interface) of the dsp563xx family of dsps from motorola. the ssi is operated in synchronous and normal mode (syn = 1 and mod = 0 in the control register b, crb) with internally generated word frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in the crb). set the word length in the control register a (cra) to 16 by setting bits wl2 = 0, wl1 = 1 and wl0 = 0 for the ad7920. this dsp does not offer the option for a 14-bit word length, so the ad7910 word length will be set to 16 bits like the ad7920. for the ad7910, the conversion process will use 16 sclk cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. to implement the power-down mode on the ad7910/ad7920, the word length can be changed to eight bits by setting bits wl2 = 0, wl1 = 0, and wl0 = 0 in cra. the fsp bit in the crb register can be set to 1, which means the frame goes low and a conversion starts. likewise, by means of bits scd2, sckd, and shfd in the crb register, it will be established that pin sc2 (the frame sync signal) and sck in the serial port will be configured as outputs and the msb will be shifted first. to summarize, mod = 0 syn = 1 wl2, wl1, wl0 depend on the word length fsl1 = 0, fsl0 = 0 fsp = 1, negative frame sync scd2 = 1 sckd = 1 shfd = 0 it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the dsp563xx provides equidistant sampling. ad7910/ad7920 * sdata sclk cs dsp563xx * sck srd sc2 * a dditional pins omitted for clarity figure 17. interfacing to the dsp563xx application hints grounding and layout the printed circuit board that houses the ad7910/ad7920 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facili tates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined at only one place. if the ad7910/ad7920 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close to the ad7910/ad7920 as possible. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7910/ad7920 to avoid noise coupling. the power supply lines to the ad7910/ad7920 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip tech nique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedi- cated to ground planes while signals are placed on the solder side. good decoupling is also very important. the supply should be decoupled with, for instance, a 680 nf 0805 to gnd. when using the sc70 package in applications where the size of the compo nents is of concern, a 220 nf 0603 capacitor, for example, could be used instead. however, in that case, the decoupling may not be as effective and may result in an approximate sinad degradation of 0.3 db. to achieve the best performance from these decoupling com- ponents, the user should endeavor to keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum with short track lengths connecting the respective pins. figures 18 and 19 show the recommended positions of the decoupling capacitor for the msop and sc70 packages respectively.
rev. b ?8 ad7910/ad7920 as can be seen in figure 18, for the msop package the decou- pling capacitor has been placed as close as possible to the ic, with short track lengths to v dd and gnd pins. the decoupling capaci- tor could also be placed on the underside of the pcb directly under- neath the ic, between the v dd and gnd pins attached by vias. this method would not be recommended on pcbs above a st andard 1.6 mm thickness. the best performance will be seen with the decou- pling capacitor on the top of the pcb next to the ic. figure 18. recommended supply decoupling scheme for the ad7910/ad7920 msop package similarly, for the sc70 package, the decoupling capacitor should be located as close as possible to the v dd and gnd pins. because of its pinout, i.e., v dd being next to gnd, the decoupling capaci- tor can be placed extremely close to the ic. the decoupling capacitor could be placed on the underside of the pcb directly under the v dd and gnd pins, but, as before, the best perfor- mance will be seen with the decoupling capacitor on the same side as the ic. figure 19. recommended supply decoupling scheme for the ad7910/ad7920 sc70 package evaluating the ad7910/ad7920 performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for con- trolling the board from the pc via the eval-board controller. to demonstrate/evaluate the ac and dc performance of the ad7910/ad7920, the evaluation board controller can be used in conjunction with the ad7910/ad7920cb evaluation boards as well as many other analog devices evaluation boards ending in the cb designator. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad 7910/ad7920 . see the evaluation board technical note for more information.
rev. b ad7910/ad7920 ?9 outline dimensions 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 3 5 4 2 6 1 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203ab 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa
?0 rev. b c02976??/04(b) ad7910/ad7920 revision history location page 3/04 ?data sheet changed from rev. a to rev. b added u.s. patent number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to note 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to note 6 of ad7920 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to note 1 of timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8/03 ?data sheet changed from rev. 0 to rev. a changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to evaluating the ad7910/ad7920 performance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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